1 Introduction

Signal processing represents, transforms, and manipulates a signal and the signal information. Signal processing technology used before 1960s was Continuous Time (CT) analog technology. But noise comes into existence in processing a signal using analog technology. Signal processing on analog circuits are even complex. But the advancement in IC technology, digital signal processing took over analog processing. The processing of signal in digital system is done using digital computation. In contrast to analog systems, the digital systems provide better reliability and resolution at a low cost. Digital systems became area efficient circuits with growth of silicon technology. Digital systems are less susceptible to noise and they add an additional feature of programmability (Brandt 1991).

Evolution of Very Large Scale Integration (VLSI) circuits led to the implementation of high performance and high resolution architectures. Digital signal processing system found its application in every field of daily life viz., consumer electronics, industrial applications, speech synthesis. Digital signal processing systems need the real-time occurring signals to be converted into digital form for processing and vice versa to get the analog output from digital processing system. Hence data converters, Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs) are required to interface the real-time analog world and the digital processing systems as in Fig. 1. Interfacing the digital domain with the analog world became the bottleneck for the designers for the processing system as lot of filtering circuits, complex conversion procedures, noise rejection and elimination circuits are involved.

Fig. 1
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Interfacing physical world with digital signal processing system

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1.1 Need for sigma delta ADC digital architecture

ADCs perform the conversion of analog to digital by different methods. By 1960s, new architectures aroused with the replacement of vacuum tubes by transistor and later by IC technology. Among various Nyquist ADCs, parallel or flash ADC is known for its high speed, Successive approximation ADC gives better accuracy but at moderate speeds. Oversampling ADCs trade digital signal processing complexity for relaxed requirements on the analog components compared to Nyquist rate ADCs. Oversampling ADCs or sigma delta architecture based on oversampling and noise shaping principles monopolized most of the applications in the last two decades (Norsworthy et al. 1996; Jacomet et al. 2004). The approach earlier by the VLSI researchers is towards Application Specific Integrated Circuit (ASIC) implementation and the analog VLSI synthesis is not automated. Research in the direction of digital implementation of the ADC is being carried out (Harsha Vardhini et al. 2012). Field Programmable Gate Array (FPGA) implementations of sigma delta ADC competed with the ASIC implementations evolving new architectures.

ASIC and FPGA implementations of sigma delta architectures allows the designers in realizing an ADC delivering reasonably good performance. But both implementations presented various limitations. Some of them are listed below.

  • Utilization of the silicon by the ADCs.

  • As the converters are placed outside the processing system they require an interface, like SPI, I2C, etc., to get connected with processing system

  • Protocol is to be followed for interfacing

  • Synchronization in multi channel ADC applications

Artigas et al. (2009) research proposed with active component digital only SD-ADC for the digitization of the parameters related to the power supply describing the dynamic comparator analysis that is carried out by implementing the negative feedback around the inverter. However, in practical FPGA circuits, possible threshold level variations of inverter gate with temperature, ageing etc. are not considered. Such unpredictable variations degrade the overall output of modulators. In low Vdd and high velocity switches these differences become more important. In addition, an FPGA input pad is used as a comparator, the hysteresis of which may produce unwanted device poles which may cause errors in the operation of signal and noise transfer (Sousa et al. 2004). The research in Palagiri et al. (2012) emphasizes the use of an LVDS input buffer as comparator on another all digital implementation. In the context of passive analog and FPGA/ASIC based SD-ADC, Jacomet et al., Fabio Sousa et al., and Artigas works are surveyed and the work proposed here describes the simulation of passive analog only SD-ADC with two high speed differential pins in Xilinx Spartan and Virtex family FPGAs. FPGA differential I/Os perform as 1 bit comparator and the digital analysis of the same can be done with spice simulations (Artigas et al. 2009; Sousa et al. 2004). FPGA configurable logic blocks can be programmed to achieve the digital block modules that perform the operation of filtering and decimation (Palagiri et al. 2012). 7 series FPGAs like ZYNQ, PYNQ with AMS technology is the motivation for the present research in the upcoming mixed signal IP technologies that provide flexibility for general purpose analog interface (Harsha Vardhini et al. 2013; Palagiri et al. 2013b).

Xilinx FPGAs are chosen due to the availability of software and tools for the simulation. However, the methodologies presented here are technology-independent, and can be applied to any FPGAs and ASIC category. The performance benchmarks are given with FPGAs made from 90 nm technology, widely used in today's systems. The approach presented in this paper presents the design of area and cost efficient sigma delta ADC with optimum performance. The second section illustrates the design of low-pass on-chip continuous-time sigma-delta ADC. Power analysis of differential I/O is carried out and tabulated in third section and fourth section illustrate the design of high speed comparator suitable for proposed architecture. The fifth section concludes the proposed work suitable for SONAR and many wireless communication applications.

2 Design of low-pass on-chip continuous-time sigma-delta ADC on FPGA

Proposed sigma delta ADC architecture suitable for signal processing applications is depicted in Fig. 2. It is a 12-bit high performance first order sigma delta ADC implemented on FPGA to overcome the limitations described in the above section.

Fig. 2
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Proposed on-chip ADC on Xilinx FPGA

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This work makes use of Xilinx FPGA to design sigma delta ADC. Conventional ASIC sigma delta modulator block is implemented here in this work with LVPECL I/O of FPGA and a resistor R and capacitor C are placed outside which are connected to the I/O, represents first order CT sigma delta modulator. Digital section following the modulator for down conversion and decimation process is implemented by the Configurable Logic Blocks (CLBs) of FPGA.

2.1 Selection of R&C

The external RC product decides the maximum input frequency. Simulations are carried out to verify the maximum input frequency for given RC value. Resistor value R is fixed, as the impedance matching needs 100 Ω termination and C is varied.

The maximum input signal frequency for LVPECL differential I/Os with various capacitor values for different voltage swings are listed in following tables. Table 1 illustrates the maximum input frequency at a various differential swing with 1 pf capacitor. Tables 2 and 3 illustrates the maximum input frequency at various input swings for LVPECL I/O with a capacitor of 10 pf and 100 pf respectively. Table 4 tabulates the same for a capacitance of 1000 pf or 1 nf. From Fig. 3, it can be interpreted that LVPECL with higher clock speed is suitable for high speed applications.

Table 1 Maximum input frequency with R = 100 Ω; C = 1 pf
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Table 2 Maximum input frequency with R = 100Ω; C = 10 pf
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Table 3 Maximum input frequency with R = 100Ω; C = 100pf
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Table 4 Maximum input frequency with R = 100Ω; C = 1000 pF or 1 nf
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Fig. 3
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Speed versus swing- various differential I/Os

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3 Power analysis of LVPECL comparator

Conventional sigma delta ADC requires comparator with faster dynamic response and stable operating conditions. FPGA differential pins can be used as comparator. Xilinx FPGA families supports various differential I/O standards viz., Low Voltage Differential Signaling (LVDS), mini LVDS, Bus LVDS, High Speed Transceiver Logic (HSTL), Reduced Swing Differential Signaling (RSDS), Low Voltage Positive Emitter coupled Logic (LVPECL), Transition Minimized Differential Signaling (TMDS), Point-to-Point Differential signaling (PPDS), so on (Harsha Vardhini and Madhavi Latha 2015; Palagiri et al. 2013a). The selected FPGA is Spartan-6 family which supports several differential signal types. Among the differential I/Os LVPECL is selected due to their fast switching speeds. The analog part and the LVPECL differential I/O simulations are carried out with H-SPICE simulator. Xilinx provided Spartan 6 I/O pad and package SPICE models are used for this simulation (Vardhini 2016). By applying various differential swings at the input to LVPECL, the performance and power is analyzed. Differential I/Os h-spice simulations are carried out and the results are illustrated in Table 5. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit for realizing 1-bit sigma delta ADC. The results are tabulated below as in Table 6 and it reports less than 1.9 mW power, which is comparable with typical low power ADC requirements. Table 6 depicts that LVPECL works at a maximum clock speed of 200 MHz and it fails to operate at a higher frequency above 200 MHz. Figure 4 depicts the power and performance analysis of LVPECL, LVDS and HSTL-II differential I/Os.

Table 5 LVPECL I/O power analysis at various differential swings
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Table 6 Power analysis of I/O standards at various differential swings
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Fig. 4
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Speed versus power

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4 Design of high speed comparator

Using a normal FPGA I/O, limits the swing of the applied input. nm-CMOS comparator with varied differential swing is designed. This section proposes a schematic level architecture of a high speed comparator which works at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads. For the future FPGAs this architecture can be implemented for high performance on-chip architecture. Comparator schematic as shown in Fig. 5 comprised of preamplifier, decision and output buffer stages. A D-flipflop and a digital buffer follow the comparator stage. Digital buffer ensure to produce the logic levels compatible to digital circuits. According to level 49 simulations, schematic extracted netlist of 130 nm model files are simulated and the results illustrate that this comparator works at 400 MHz clock.

Fig. 5
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Comparator schematic

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4.1 CIC based decimator with 1-bit input at these high rates in digital fabrics

CIC architecture is as shown in Fig. 6 where by the down sampling by a factor of D is carried out by integrators before comb sections. A total decimation of 400 is achieved out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining factor of 4. Proposed sigma delta ADC top level functionality is verified by Analog Mixed Signal VHDL. The analog and digital sections and mixed signal simulations at different stages are carried out and compared with the work contributed by Sousa et al. (2004) using FPGA I/O pads with LVDS as a comparator for SD-ADC in Table 7.

Fig. 6
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Digital section

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Table 7 Comparison of results of proposed SD-ADC with Sousa et al. (2004)
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Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for input signal of 1 MHz with output data rate of is 1 MHz with a dynamic range of 72 dB.

4.2 Applications

On-chip sigma-delta ADC architecture with FPGA differential I/Os find its applications including low cost instrumentation, audio, SONAR and sensor networks. Among several applications the sigma delta ADC architectures are highly suitable for many wireless applications where ADC is a requisite and the count of ADCs needed by the application is more in number. Wireless applications, RADAR, SONAR applications can be easily benefitted with the proposed architecture due to the advantages over existing categories (Palagiri et al. 2016; Bindu Tushara and Harsha Vardhini 2015). Firstly, SONAR beamforming applications require digitization of SONAR signals coming from multiple sensors with high level of time synchronization. Multi channel inputs where analog to digital conversion is required can be replaced with proposed architecture (Bindu et al. 2017; Szczesny et al. 2020).

Secondly, for low cost wireless sensor networks, wireless transceivers infrastructure for industrial automation and sensor networks where analog to digital converters are extensively used in current and future automation topologies, there is a constant effort to evolve low cost wireless nodes (Hu et al. 2019; Harsha Vardhini and Murali Mohan Babu 2020). The proposed on-chip ADC is suitable for wireless transceivers with required bandwidth access. IoT based wireless applications implemented with arduino, raspberry pi or any controller boards with ‘n’ number of sensor and ADCs can be replaced with the proposed on-chip ADC FPGA architecture (Babu and Harsha Vardhini 2020; Harsha Vardhini et al. 2020; Vasishta et al. 2020).

5 Conclusion

On-chip sigma delta ADC with the Xilinx FPGA differential I/O i.e., LVPECL is analyzed and the on-chip architecture is simulated with the proposed comparator design. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed ADC exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted 1.86 mW for input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves decimation factor of 4. Output data rate of is 1 MHz with a dynamic range of 72 dB. SONAR/RADAR applications utilizing the maximum silicon area for analog to digital conversion of the real time signals can be easily achieved by replacing the proposed architecture with the existing FPGA architecture differential I/Os. Proposed On-chip sigma delta ADC design enable high end signal processing application realization with less bill of material.