DEVELOP A LIBRARY SYSTEMVERILOG ASSERTIONS (SVA) FOR AN AXI INTERFACE PROTOCOL

Abstract: The primary goal of this project is to ensure that sophisticated extensible interface features work as intended (AXI). There are five channels—write address, write data, write response, read address, and read data—that must be verified in order to ensure the integrity of AXI memory operations. Read and write transactions to and from the same and distinct memory locations are modeled in Verilog in this design. Data transmissions can be either single or many bursts in length, as specified by the design implementation. Memory read and write channels are provided via the AXI protocol. AXI protocol with 32-bit SARM is used to facilitate communication between a master and a slave in this work. When creating verification IP, a System Verilog-based verification environment is built up and employed. Meanwhile, the AXI protocol's capabilities are being tested using SV Assertion-based verification. AMBA AXI, Bus Function Model (BFM), Design Under Test (DUT), Network on Chip (NOC), SOC Integration, SV Assertion, Verification IP are some of the terms that can be found in an AMBA AXI-related index. Design, assertions, and the testbench are
the three main pillars of the System Verilog language. When it comes to verifying ASICs, assertions introduce a new dimension. Proactive verification is simplified with the use of assertions. Engineers are accustomed to creating design simulations through the usage of verilog test benches. Since it is a procedural language, Verilog's capabilities are limited when it comes to dealing with the complexity of modern ASICs.
Keywords- Verilog, ASICS, RTL, FPGA